1. Field of the Invention
The present invention relates to a logic circuit in a CMOS semiconductor integrated circuit etc., more particularly relates to a logic circuit serving as a flip-flop with an embedded logic function combining the functions of a 1-bit storage element operating in synchronization with a synchronization signal, that is, a flip-flop, and several logic gates located at its data input packaged into one unit.
2. Description of the Related Art
An integrated circuit generally performs a logical operation by a combination of logic gates and stores the results thereof in a flip-flop for use for the operation of the next cycle.
For example, structures very common in integrated circuits such as sequential circuits and pipelines are also configured by flip-flops and one or more logic gates arranged at the data input thereof.
Below, an explanation will be made of first to fourth conventional examples of a circuit comprised of a flip-flop and one or more logic gates arranged at the data input thereof.
First Conventional Example
FIG. 1 is a view of a first conventional example realizing a general structure of a flip-flop and logic gates arranged at the data input thereof by a static CMOS logic circuit 10.
As shown in FIG. 1, the desired logical function is realized by a combinational logic circuit LC11. A logical function output F11 thereof is supplied to a data input D of a flip-flop FF11.
In the flip-flop FF11, a value of the input D is fetched in synchronization with a synchronization signal CLK and output from a data output Q.
FIG. 2 is a circuit diagram of a transistor level of the flip-flop FF11.
The flip-flop FF11 shown in FIG. 2 is based on a master-slave type flip-flop using a CMOS transmission gate disclosed in John P. Uyemura, CMOS LOGIC Circuit Design, Kluwer Academic Publishers, pp. 278-281, 1999 and is being generally used at the present.
Specifically, the flip-flop FF11 of FIG. 2 has inverters INV11 to INV18 and CMOS transmission gates TMG11 and TMG12.
Further, FIG. 3 is a circuit diagram of an example of the configuration of the combinational logic circuit LC11.
This logic circuit LC11 has a 2-input exclusive OR gate (EXOR) ER11, a 2-input exclusive negative OR gate (EXNOR) ENR11, and a 2-input NAND gate NA11.
A logic circuit LC1 of FIG. 3 shows a case where the logical function F=A(+){(B(+)C)xc2x7D} is realized.
Second Conventional Example
Further, the idea itself of combining the functions of a flip-flop and several logic gates located at its data input into one package has been already disclosed.
As a first example thereof, there is a PDN (pull down network) mounted type flip-flop of the AMD Co. (below, simply referred to as a xe2x80x9cPDN-F/Fxe2x80x9d) (refer to Steven Hesley et al., xe2x80x9cA 7th-Generation xc3x9786 Microprocessorxe2x80x9d, ISSCC DIgest of Technical Papers, pp. 92-93, February 1999, or Alisa Scherer et al., xe2x80x9cAn Out-of-Order Three-Way Superscalar Multimedia Floating-Pointxe2x80x9d, ISSCC Digest of Technical Papers, pp. 282-283, February 1999).
FIG. 4 is a circuit diagram of the general configuration of a PDN-F/F, and FIG. 5 is a circuit diagram of a concrete example of the configuration of a PDN-F/F logic circuit mounting a logical function of one multiplexer.
The PDN-F/F logic circuit 20 is configured by a dynamic circuit unit 21 comprising p-channel MOS (PMOS) transistors PT21 and PT22 and n-channel MOS (NMOS) transistors NT11 to NN13 and by a static circuit unit 22 comprising inverters INV21 and INV22 with inputs and outputs connected with each other and configuring a latch and an output use inverter INV23.
PDN is an abbreviation of a xe2x80x9cpull down networkxe2x80x9d as mentioned above and is what is generally referred to as an NMOS single-rail type logic tree 23.
In this system, the dynamic circuit unit 21 evaluates the logic, and the value thereof is held by the latch of the static circuit unit 22.
The characterizing feature of the PDN-F/F logic circuit 20 resides in that a pulsed clock PCLK to be input to the PMOS transistor PT21 and an NMOS transistor NT21 must be a short width pulse which is generated in synchronization with the rising of the global synchronization signal CLK.
The pulsed clock PCLK is generated by a pulse generator 24 as shown in FIG. 5.
This pulse generator 24 is configured by an inverter INV24 to which a clock inverted signal CLK_X is input, a PMOS transistor PT23 and NMOS transistors NT24 and NT25 connected in series between a supply line of a power source voltage VDD and a ground and having gates to which the output of the inverter INV24 is supplied, a 2-input NAND gate NA21 to which a potential of a connection point of drains of the PMOS transistor PT23 and the NMOS transistor NT24 and an enable signal ENB are input, and a 2-input NOR gate NR21 to which the output of the NAND gate NA21 and the clock inverted signal CLK_X are input.
When the pulsed clock PCLK has a logic xe2x80x9c0xe2x80x9d, an internal node F is initialized to a logic xe2x80x9c1xe2x80x9d.
When the pulsed clock PCLK becomes the logic xe2x80x9c1xe2x80x9d, the logic is evaluated in the logic tree (PDN) 23, and the node F changes. This change is transferred to the latch 22a comprising the inverters INV21 and INV22 through a dynamic inverter configured by the PMOS transistor PT22 and NMOS transistors NT23 and NT24. During this period, the input signal must not change.
The important thing in the PDN-F/F logic circuit 20 is that the time during which the pulsed clock PCLK becomes the logic xe2x80x9c0xe2x80x9d is precisely controlled.
This time must be the minimum time long enough for a change of the potential of the node F from the logic xe2x80x9c1xe2x80x9d to the logic xe2x80x9c0xe2x80x9d.
If it is too short, the potential ends up returning to logic xe2x80x9c1xe2x80x9d again while F does not sufficiently change to the logic xe2x80x9c0xe2x80x9d, so the logic cannot be correctly evaluated. If it is too long, however, the time during which the input signal cannot change becomes long.
As the times during which the input must not change at a time of operation, even in a general flip-flop, there are a set-up time and a hold time. It generally is regarded that a shorter time means better performance.
The time during which the pulsed clock PCLK becomes the logic xe2x80x9c1xe2x80x9d is directly related to the set-up time and the hold time in the PDN-F/F logic circuit 20, so a shorter width of the pulsed clock PCLK is preferred.
The characterizing feature of the pulse generator 24 shown in FIG. 5 generating the pulsed clock PCLK resides in that an adequate width of the pulsed clock PCLK is obtained by the NMOS transistors NT24 and NT25.
When the PDN, that is, the logic tree 23, becomes three NMOS""s in size, that is, if another NMOS transistor is added in series in addition to the NMOS transistors NT24 and NT25, it becomes possible to generate three NMOS""s worth of delay in the pulse generator 24.
It is considered that the main object of the PDN-F/F logic circuit 20 resides in the realization of a high speed logic circuit.
In general, a circuit realized by a dynamic logic circuit is higher in speed than one realized by a static logic circuit.
Further, in the PDN-F/F logic circuit 20, the master latch and the logic tree are combined with the aim of shortening the set-up time and the hold time relating to the input terminal of the logical functions.
Third Conventional Example
As a second example of the idea of combining the functions of a flip-flop and several logic gates located at its data input into one package, a sense amplifier-based flip-flop (hereinafter simply referred to as an xe2x80x9cSA-F/Fxe2x80x9d) may be mentioned (see Borivoje Nikolic et al., xe2x80x9cSense Amplifier-Based Flip-Flopxe2x80x9d, ISSCC Digest of Technical Papers, pp. 282-283, February 1999 or R. Stephany et al., xe2x80x9cA 200 MHZ 32 b 0.5 W CMOS RISC Microprocessorxe2x80x9d, ISSCC Digest of Technical Papers, pp. 238-239, February 1998).
FIG. 6 is a circuit diagram of the general configuration of an SA-F/F logic circuit, while FIG. 7 is a circuit diagram of a concrete example of the configuration of a SA-F/F logic circuit mounting the logical function of one multiplexer.
An SA-F/F logic circuit 30 is configured by an NMOS dual-rail type logic tree 31 including NMOS transistors NT301 to NT316, an NMOS transistor NT31 for controlling the connection of the NMOS dual-rail type logic tree 31 to the ground in synchronization with the clock signal CLK, a sense amplifier 32 configured by PMOS transistors PT31 to PT34, and NMOS transistors NT32 to NT34, and a NAND type SR latch 33 configured by NAND gates NA31 and NA32.
Note that the gate terminal of the NMOS transistor NT34 in the sense amplifier 32 is connected to the supply line of the power source voltage VDD and is always in the ON state.
In the SA-F/F logic circuit 30, when the synchronization signal CLK has the logic xe2x80x9c0xe2x80x9d, the precharging by the PMOS transistors PT31 and PT32 of the sense amplifier 32 is carried out. By this, both of the logic output nodes TH and TH_X with respect to the SR latch 33 become the logic xe2x80x9c1xe2x80x9d and the outputs thereof are held.
The logic inputs F and F_X by the logic tree 31 are precharged to a voltage lower than the potential of the logic xe2x80x9c1xe2x80x9d by the amount of the threshold value of the NMOS transistor through the NMOS transistors NT32 and NT33.
At this time, since the NMOS transistor NT31 is out off, a passing-through current does not flow.
When the clock signal CLK becomes the logic xe2x80x9c1xe2x80x9d, the PMOS transistors PT31 and PT32 become OFF, the NMOS transistor NT31 becomes ON, and the logic evaluation is commenced.
According to the input signal, a path through which one of the logic input node TF and TF_X with respect to the sense amplifier 32 reaches the ground is formed in the logic tree 31. Here, it is assumed that this is the logic input node TF side.
In this case, the potential of the logic input node TF quickly drops to the logic xe2x80x9c0xe2x80x9d.
Here, the NMOS transistor NT34 of the sense amplifier 32 is always ON and behaves like a real resistor, therefore the charge at the logic input node TF_X flows to the logic input node TF side through the NMOS transistor NT34.
Accordingly, the potential of the logic input F_X also drops to xe2x80x9c0xe2x80x9d with a slight delay after the logic input F.
Finally, both of the potentials of the logic inputs F and F_X drop to the potential of the logic xe2x80x9c0xe2x80x9d, but the logic outputs H and H_X do not. Here, it is assumed that H=0 and H_X=1.
When the logic input F first drops to the logic xe2x80x9c0xe2x80x9d, the logic output H also becomes the logic xe2x80x9c0xe2x80x9d through the NMOS transistor NT32.
However, the logic output node TH_X recovers to the logic xe2x80x9c1xe2x80x9d after the potential falls a little. This is because since the logic input F drops to the logic xe2x80x9c0xe2x80x9d slightly earlier, the PMOS transistor PT34 becomes ON and a charge is supplied to the logic output node TH_X. Due to this, the PMOS transistor PT33 and NMOS transistor NT33 cut off, the PMOS transistor PT34 and NMOS transistor NT32 become ON, and a stable paired logic potential state is maintained at the logic output nodes TH and TH_X.
These two logic outputs H and H_X are also the inputs of the SR latch 33, therefore, here, the evaluation result of the logical function is inserted and output to the SR latch 33.
Even if a change occurs in the input signal after this and the path reaching the ground in the logic tree 31 changes from the logic input F to F_X, there is no effect upon the operation.
This is because the NMOS transistor NT33 has already become cut off and the charge of the node TH_X will not flow to the logic input node TF_X side. The path of the ground reaching the logic input node TF_X still only fixes the potential of the node TH at the logic xe2x80x9c0xe2x80x9d through the NMOS transistors NT34 and NT32.
It is considered that the main object of the SA-F/F logic circuit 30 also resides in the realization of a high speed logic circuit in the same way as the PDN-F/F logic circuit 20.
The SA-F/F logic circuit 30 evaluates a logical function by the dynamic logic circuit in the same way as the PDN-F/F logic circuit and combines a sense amplifier and master latch with the aim of shortening the set-up time and the hold time relating to the input terminal of the logical functions.
Fourth Conventional Example
As a third example of the idea of combining the functions of a flip-flop and several logic gates located at its data input into one package, the differential current switch logic (hereinafter simply referred to as a xe2x80x9cDCSLxe2x80x9d) circuit may be mentioned (see Dinesh Somasekhar et al., xe2x80x9cDifferential Current Switch Logic: A Low Power DCVS Logic Familyxe2x80x9d, IEEE JSSC, vol. 31, no. 7, pp. 981-991, July 1996).
FIG. 8 is a circuit diagram of the general configuration of a DCSL circuit.
A DCSL circuit 40 is configured by, in the same way as the SA-F/F logic circuit 30, an NMOS dual-rail type logic tree portion 41, a sense amplifier unit 42 configured by PMOS transistors PT41 to PT43 and NMOS transistors NT41 to NT45, and a NOR type SR latch 43 configured by NOR gates NR41 and NR42.
In the same document, three types of sense amplifiers (DCSL1, DCSL2, and DCSL3) are proposed (pp. 983, FIGS. 4 to 6). Here, the DCSL3 will be taken up. Further, as in the document, the DCSL itself is a proposal relating to method of configuration of a new dynamic logic circuit, particularly the sense amplifier system, and is not aimed at the realization of a flip-flop with an embedded logical function. However, the same document, pp. 986, FIG. 12 introduces xe2x80x9ca Latched DCSL output statexe2x80x9d and suggests the realization of a flip-flop with an embedded logical function.
Unlike the SA-F/F logic circuit, in the DCSL (DCSL3) circuit 40, as the initial state of the flip-flop operation, the potentials of the logic outputs H and H_X of the sense amplifier 41 are set in the vicinity of the threshold voltage of the NMOS transistor. The potentials are treated as the logic xe2x80x9c0xe2x80x9d for the later logic gates referring to them.
In the initial state of the flip-flop operation, the clock inverted signal CLK_X is supplied with the logic xe2x80x9c1xe2x80x9d, the PMOS transistor PT41 cuts off, and the NMOS transistor NT45 becomes ON.
Since the NMOS transistor NT45 becomes ON, the internal nodes TH and TH_X are short-circuited. This means that all of the gate terminals and drain terminals of the NMOS transistors NT41, NT42, NT43, and NT44 are short-circuited.
A MOS transistor in which the gate terminal and the drain terminal are short-circuited behaves equivalently to a diode.
Here, a case where the logic potentials of the nodes TH and TH_X immediately before the clock inverted signal CLK_X becomes the logic xe2x80x9c1xe2x80x9d are [0,1] will be considered. In this case, a positive charge is stored at the node TH_X.
When the clock inverted signal CLK_X becomes the logic xe2x80x9c1xe2x80x9d and the short-circuiting by the NMOS transistor NT45 occurs, the charge at the node TH_X starts to flow to the node TH resulting in balanced distribution.
At this time, if the charge does not flow elsewhere, the potentials of the two nodes TH and TH_X become half of the power source voltage VDD.
However, as mentioned above, the NMOS transistors NT41, NT42, NT43, and NT44 at this time behave as diodes, therefore the current flows until the potential difference between the two ends of the diode becomes substantially equal to the threshold value of the NMOS transistor.
Specifically, the NMOS transistors NT41 and NT42 pass current to the ground, while the NMOS transistors NT43 and NT44 pass current to the logic output nodes TF and TF_X of the logic tree 41.
In this way, the potentials of the nodes TH and TH_X become substantially equal to the threshold value of the NMOS transistor.
At this time, even if one of the nodes TF and TF_X of the logic tree 41 has a path reaching the ground, there is no outflow of potential from the nodes TH and TH_X.
This is because the voltages added to the gate terminals of the NMOS transistors NT43 and NT44 are in the vicinity of the threshold value of the NMOS transistor and the transistors have cut off.
Accordingly, the potentials at the nodes TF and TF_X become unstable. In most cases, however, they become values near the potential of the logic xe2x80x9c0xe2x80x9d.
The potentials of the nodes TH and TH_X are in the vicinity of the threshold voltage of the NMOS transistor. They are treated as the logic xe2x80x9c0xe2x80x9d, so the NOR type SR latch 443 holds the output thereof.
The clock inverted signal CLK_X becomes the logic xe2x80x9c0xe2x80x9d (this is equivalent to the rising of the clock signal CLK), and the logic evaluation is commenced.
In this case, the NMOS transistor NT45 cuts off, the short-circuited state heretofore disappears, the PMOS transistor PT41 becomes ON, and the current starts to flow.
Since a voltage in the vicinity of the threshold value of the NMOS transistor has been added to the gate terminals of the PMOS transistors PT42 and PT43, the PMOS transistors PT42 and PT43 start from the ON state.
Accordingly, a charge is supplied to the nodes TH and TH_X through these PMOS transistors PT41, PT42, and PT43.
The NMOS transistors NT43 and NT44 start from the cut-off state since a voltage in the vicinity of the threshold value of the NMOS transistor has been added to the gate terminals (that is, the nodes TH and TH_X).
The charge is supplied to the nodes TH and TH_X, these node potentials rise, and the NMOS transistors NT43 and NT44 weakly start to become ON.
In the same way as the SA-F/F logic circuit, a path reaching the ground is always formed in one of the logic output nodes TF and TF_X of the logic tree by the combination of the input signals. This is assumed to be TF here.
Current flows from the node TH toward the node TF through the NMOS transistor NT43 which weakly starts to become ON. The potential of the node TH which has been starting to rise is dropped to the potential of the complete logic xe2x80x9c0xe2x80x9d.
Since the node TH becomes the potential of the complete logic xe2x80x9c0xe2x80x9d, the PMOS transistor PT43 becomes completely ON, and the NMOS transistors NT42 and NT45 become completely cut off.
For this reason, the node TH_X quickly reaches the potential of the complete logic xe2x80x9c1xe2x80x9d. Further, simultaneously, the PMOS transistor PT42 becomes completely cut off, and the NMOS transistors NT41 and NT43 become completely ON.
By this, the stable paired logic potential state is maintained at the nodes TH and TH_X. The logic outputs H and H_X corresponding to the potentials of these two nodes are also the inputs of the SR latch 43, so the evaluation result of the logical function is inserted and output to the SR latch 43 here.
Even if a change occurs in the input signal thereafter and the path reaching the ground in the logic tree 41 changes from the node TF to TF_X, there is no effect on the operation.
The NMOS transistor NT44 has already become cut off and current will not flow from the node TH_X to the node TF_X. Further, even if the node TF no longer has a path reaching the ground, the NMOS transistor NT41 has become ON and maintains the node TH at the complete logic xe2x80x9c0xe2x80x9d.
One of the objects of the DCSL circuit 40 resides in the realization of a high speed logic circuit in the same way as the SA-F/F logic circuit. Further, simultaneously realizing a reduction in the power consumption has also become one of the major objects.
In the DCSL circuit 40, the current flowing into the logic tree 41 is controlled by the NMOS transistors NT43 and NT44.
As mentioned above, the NMOS transistor at the side which becomes the logic xe2x80x9c1xe2x80x9d in the process of the logic evaluation becomes out off.
For this reason, the potentials of the logic output nodes TF and TF_X of the logic tree 41 only slightly rise from the potential of the logic xe2x80x9c0xe2x80x9d. A slight potential amplitude of the logic output nodes TF and TF_X of the logic tree 41 means that the potential amplitude at the node inside the logic tree is further smaller than this.
The power consumption is proportional to a square of the logic amplitude, therefore the power consumption of the logic tree portion is extremely small in comparison with the SA-F/F logic circuit using the same NMOS dual-rail type logic tree.
Further, in the SA-F/F logic circuit, the higher the logic tree, the larger the time up to the final determination of the logic.
In the DCSL circuit, however, the dependency of the logic determination time with respect to the height of the logic tree is small (above document, pp. 989, FIG. 18). This is also because of the fact that the NMOS transistors NT42 and NT44 become cut off before too much current flows into the logic tree 41.
The logic is determined at the sense amplifier 42 side before the logic output nodes TF and TF_X of the logic tree 41 fluctuate that much, therefore the DCSL circuit by nature is resistant to the effect of the height of the logic tree in comparison with the SA-F/F logic circuit in which the nodes of the logic tree largely fluctuate.
However, the circuits of the first to fourth conventional examples mentioned above have the following problems.
Problems of First Conventional Example
One of the problems of the static CMOS logic circuit explained as the first conventional example is the large power consumption due to glitches.
A xe2x80x9cglitchxe2x80x9d means an incorrect signal transition occurring transitorily at an output node or an intermediate node of the combinational logic circuit.
In the CMOS logic circuit, a power consumption P thereof is given by the following equation where a signal frequency is f, a gate capacity, an interconnection capacity, etc. are C, and a signal amplitude potential is V.
P=fxc2x7Cxc2x7V2xe2x80x83xe2x80x83(1)
When a glitch occurs, the signal frequency seemingly becomes large, and the power consumption is increased from the relationship of the above (1).
Below, an explanation will be made of factors behind the occurrence of glitches in relation to FIGS. 9A and 9B.
In FIGS. 9A and 9B, it is assumed that initial logic potentials of the input signals A, B, C, and D are xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, and xe2x80x9c1xe2x80x9d, and the logic potential of the logical function output F has been fixed to xe2x80x9c1xe2x80x9d. Further, it is assumed that the transition of the input signal does not occur simultaneously at A, B, C, and D, but occurs in an order of A, B, C, and D as illustrated.
When the input signal A becomes the logic xe2x80x9c1xe2x80x9d, the logical function output F11 of the logic circuit LC11 shifts to the logic xe2x80x9c0xe2x80x9d. Next, when the input signal B becomes the logic xe2x80x9c1xe2x80x9d, the logical function output F11 shifts to the logic xe2x80x9c1xe2x80x9d. Further, when the input signal C becomes the logic xe2x80x9c0xe2x80x9d, the logical function output F11 shifts to the logic xe2x80x9c0xe2x80x9d. Finally, when the input signal D becomes the logic xe2x80x9c0xe2x80x9d, the logical function output F11 shifts to the logic xe2x80x9c1xe2x80x9d.
The signal transition of the logical function output F11 carried out here is the correct evaluation result output according to the change of the input signal at that instant. There is no error contained in individual signal transitions per se.
However, the initial value of the logical function output F11 is xe2x80x9c1xe2x80x9d and also finally becomes xe2x80x9c1xe2x80x9d, therefore signal transition during this time is not required, so it still should be called an incorrect signal.
Further, a glitch may occur even if the transitions of the input signals simultaneously occur. It is assumed that the logic potentials at the nodes at a time t are represented as A(t)=1. Further, it is assumed that the outputs of the logic gates are determined by the one past input, for example, as follows:
R(t)=B(txe2x88x921)(+)C(txe2x88x921)xe2x80x83xe2x80x83(2)
In equation (2), in the initial state where t=0,
Input signal: A(0)=0, B(0)=0, C(0)=1, D(0)=1,
Intermediate node: R(0)=1, S(0)=0,
Output node: F(0)=1.
When t=1, the input signals shift all together,
Input signal: A(1)=1, B(1)=1, C(1)=0, D(1)=0,
Intermediate node: R(1)=1, S(1)=0,
Output node: F(1)=1.
When t=2,
Input signal: A(2)=1, B(2)=1, C(2)=0, D(2)=0,
Intermediate node: R(2)=1, S(2)={circumflex over ( )}R(1)xc2x7D(1))=1,
Output node: F(2)={circumflex over ( )}(A(1)(+)S(1))=0.
When t=3,
Input signal: A(3)=1, B(3)=1, C(3)=0, D(3)=0,
Intermediate node: R(3)=1, S(3)={circumflex over ( )}(R(2)xc2x7D(2))=1,
Output node: F(3)={circumflex over ( )}(A(2)(+)S(2))=0.
After this, it becomes constant. Note that indicates inversion.
As described above, the logical function output F shifts in the manner of 1xe2x86x920xe2x86x921. Even if the input signals are simultaneously given, glitches occur.
This is caused due to the difference of the number of the logic gates of the internal portion. The inputs of the circuit as a whole are A, B, C, and D, but the inputs of the logic gate ENR11 itself in FIG. 3 are the input signal A and the output signal S of the logic gate NA11. The change of the signal S occurs after the logic gate ER11 changes due to the change of the input signals B and C, therefore the phases of the changes of the signal A and the signal S do not become equal.
Accordingly, when viewing the inputs of the gates, there are still differences in the signal transitions thereof and as a result glitches may occur.
In examples heretofore, there were no glitches in the input signals. The glitches occurred due to the time difference of the changes of the input signals and the intermediate signals. Such a glitch will be particularly referred to as a xe2x80x9cgeneration glitchxe2x80x9d.
On the other hand, there is something called a xe2x80x9cpropagation glitchxe2x80x9d produced by a glitch contained in the input signal.
In FIGS. 9A and 9B, when the input signal D=1, the logical function to be realized becomes F11=A(+)B(+)C. Even if two among the three input signals are fixed to certain logic values, if there is a glitch in the remaining one input, a glitch also occurs at the output F11.
For example, when a glitch is generated at A and there is a change of 0xe2x86x921xe2x86x920, irrespective of the case where originally A=B=C=0, the output F11 also changes as 0xe2x86x921xe2x86x920.
As described above, the factors behind the generation of a glitch are, first, the variation of the transition time of the input signals, second, the variation of the input transitions of individual logic gates due to the delay difference produced inside the combinational logic circuit, and, third, the glitch contained in the input signals.
In all cases where a glitch occurs due to these three factors, the logic circuit outputs the correct logic value according to the input signal at that instant. The logic circuit itself cannot determine that it is outputting an incorrect value at that instant.
To eliminate the first and second factors, the method of inserting a very precise delay element onto the internal signal line for adjustment so that the signal changes with respect to all logic gate inputs of the internal portion become aligned and, to eliminate the third factor, the method of using two signal lines for expressing a 1-bit logic value for determining the logic while judging the validity/invalidity of the signal are being considered.
However, these methods are not practical for the reasons that realization is difficult, the hardware cost is increased, and power ends up being consumed more than the reduction of the glitches.
Therefore, it is in principle difficult to completely eliminate glitches in a general static CMOS logic circuit, which makes this impractical.
Problems of Second Conventional Example
The biggest feature among the characteristic features of the PDN-F/F logic circuit 20 explained as the second conventional example is the mechanism for generating the pulsed clock PCLK (pulse generator 24 in FIG. 3).
In principle, if the number of the serially connected NMOS transistors (height) of the pulse generator 24 is adjusted to match with the height of the PDN, that is, the logic tree 23, the optimum width of the pulsed clock PCLK is obtained.
In actuality, however, even if the heights are the same, the sizes in the lateral direction differ, therefore correct reproduction of the speed of change of the node TF in the PDN inside the pulse generator 24 is impossible. Enlargement of the size in the lateral direction means the enlargement of the junction capacity and the interconnection capacity of the MOS.
Further, when the pulse generator 24 is separated from the body of the PDN-F/F logic circuit 20 as a separate cell, there will also be a metal interconnection passing through the interconnection layer between the pulsed clock output terminal of the pulse generator 24 and the pulsed clock input terminal of the PDN-F/F logic circuit body.
In LSI design, generally the placement and routing of the cells are automatically performed by CAD. At this time, the lengths of the interconnections between cells made by the CAD are not constant. It is also difficult to predict them in advance.
When such a design technique is applied to a PDN-F/F logic circuit, the interconnection length of the pulsed clock PCLK extending from the pulse generator 24 changes for every design. A metal interconnection has a parasitic capacitance and the size thereof is generally proportional to the interconnection length, therefore the load connected to the pulsed clock output terminal of the pulse generator 24 changes for every design.
Whenever the interconnection load changes, the width of the pulsed clock PCLK will always also change. The amplitude of the pulsed clock PCLK is the element directly determining the set-up time and the hold time of the PDN-F/F logic circuit.
Therefore, a PDN-F/F logic circuit will not have a constant set-up time and hold time when the placement and routing are performed by CAD. The set-up time and the hold time are values important in LSI design utilized for timing analysis etc. If the correct values cannot be found before the actual placement and routing, the circuit will never be practical.
On the other hand, when the pulse generator 24 is combined with the PDN-F/F logic circuit to form a single cell, the large size of the circuit of the pulse generator 24 becomes a problem.
An SA-F/F logic circuit does not have anything corresponding to the pulse generator 24, but the logic tree is not a single-rail type, but a double-rail type paired logic tree.
The circuit of the logic tree becomes about twice the size in the case of an SA-F/F logic circuit, but if considering the circuit size of the pulse generator 24, the SA-F/F logic circuit often ends up becoming more compact.
Problems of Third Conventional Example
The problem of the SA-F/F logic circuit 30 explained as the third conventional example is that the time until the final determination of the logic closely depends upon the charge discharging speed of the NMOS logic tree.
The nodes TF and TF_X in FIG. 6 are precharged to potentials lower than the potential of the logic xe2x80x9c1xe2x80x9d by exactly the amount of the threshold value of the NMOS transistor before the commencement of the logic evaluation.
Together with the commencement of the logic evaluation, the charges are discharged through the NMOS logic tree 31. Both of the potentials of the two nodes TF and TF_X finally become the potential of the logic xe2x80x9c0xe2x80x9d, but one of them always reaches the logic xe2x80x9c0xe2x80x9d earlier than the other. The node. which becomes the logic xe2x80x9c0xe2x80x9d earlier is the one related to the final determination of the logic.
The time by which the node reaches the potential of the logic xe2x80x9c0xe2x80x9d is generally determined by a resistance R of the NMOS transistor on the path reaching the ground and the capacity component C inside the logic tree 31 when simply considering the NMOS transistor which has become ON as a resistor.
Simply speaking, the time for reaching the logic xe2x80x9c0xe2x80x9d potential is proportional to (total Rxc2x7total C). When the gate width of the NMOS transistor is Wn and the gate length is Ln, the ON resistance R thereof is proportional to (Ln/Wn).
When the number of transistors on the path from the end point of the logic tree to the ground, that is, the height of the logic tree, is h, it can be considered that the total R is proportional to (h/Wn). Here, in general, Ln is a fixed value determined by the manufacturing process, so is omitted.
The total C includes a diffusion capacitance of the NMOS inside the logic tree 31 etc. and is in a relationship of a monotonic increase with respect to the height h of the logic tree.
Accordingly, the time for final determination of the logic of the SA-F/F logic circuit 30 is generally proportional to the height h of the NMOS logic tree and generally inversely proportional to the gate width Wn.
The height of the logic tree is substantially equal to the number of the input signals of the logical function to be realized. For example, if it is a 5-input EXOR, the height of the logic tree becomes 5.
Therefore, the more complex the logical function (the larger the number of input signals), the longer the time for final determination of the logic of the SA-F/F logic circuit.
When it is intended to reduce the prolongation of the time for final determination of the logic in this way, the gate width Wn of the NMOS transistor inside the logic tree 31 is made larger so as to make the ON resistance R smaller. The NMOS transistor has a capacity component proportional to (Wnxc2x7Ln) when seen from the side driving the gate terminal thereof. As mentioned above, the power consumption is proportional to the capacity component of the system.
Therefore, in an SA-F/F logic circuit 30, an increase of speed and a reduction of the power consumption cannot be achieved simultaneously.
Problems of Fourth Conventional Example The DCSL circuit 40 explained as the fourth conventional example is remarkably susceptible to fluctuations in the circuit constants, noise, etc. as pointed out by itself in the above reference.
In the initial state of the operation of the flip-flop, the nodes TH and TH_X inside the sense amplifier 32 are short-circuited and initialized to the voltage near the NMOS threshold value.
When the clock inverted signal CLK_X becomes the logic xe2x80x9c0xe2x80x9d (when the CLK rises), both nodes are cut off, a difference occurs in the potentials of the nodes TH and TH_X according to the magnitudes of the currents flowing into the nodes TF and TF_X of the logic tree and is expanded by the inverter pair comprising the PMOS transistors PT42 and PT43 and the NMOS transistors NT41 and NT42, and the logic value is thus finally determined.
If an incorrect potential fluctuation due to the coupling noise or the like occurs at either of the nodes H and H_X in this process, an erroneous logic value is liable to be finally determined. Even if that incorrect potential fluctuation is very weak (about {fraction (1/10)} to {fraction (1/20)} of the logic amplitude), the potential fluctuations of the nodes TH and TH_X at the commencement of the operation are also small, therefore nodes are susceptible to their influence.
For example, consider the case where the correct logic value determination becomes H=0 and H_X=1 and noise lifting the potential of the node TH is added to it.
The logic tree node TF has a path reaching the ground. The charge on the node TH is drawn out through the NMOS transistor NT43.
However, the voltage applied to the gate terminal of this NMOS transistor NT43 is nothing other than the potential of the node TH_X and is a voltage of an extent that is a little larger than the vicinity of the threshold value of the NMOS transistor.
For this reason, the NMOS transistor NT43 does not become sufficiently ON, and a conduction resistance thereof is considerably large. Accordingly, the incorrect potential fluctuation rising due to the noise cannot be immediately reduced. Where the potential of the node TH at that time is larger than the potential of the node TH_X, the logic value is defined to H=0 and H_X=1 by the function of the sense amplifier 42.
Even when there is no coupling noise, an erroneous logic value is sometimes finally determined due to the variation of the circuit constant.
For example, consider a case where a parasitic capacitance connects to the node TH is smaller than that of the node TH_X even in the case where the correct logic value determination becomes H=0 and H_X=1.
At the commencement of the operation of the flip-flop, the potentials of both nodes slightly rise due to the charges supplied through the PMOS transistors PT41 to PT43.
Since the logic tree node TF has a path reaching the ground, when the correct logic is finally determined, the method of the rise of the node TH becomes slower than that of the node TH_X.
The potential difference produced in this way is enlarged at the sense amplifier 42 and finally determined to the correct logic value.
However, when there is a remarkable difference in the parasitic capacitances connected to the nodes TH and TH_X and the node TH_X is larger, the node TH_X rises slower than the node TH.
Originally, the charge supplied to the node TH is drawn out to the logic tree 41 through the NMOS transistor NT43, so must be held at a potential lower than the node TH_X.
As mentioned above, however, the NMOS transistor NT43 has not sufficiently become ON, the conduction resistance thereof is considerably large, and the difference of the parasitic capacitances cannot be sufficiently absorbed.
In this way, there is a phenomenon of the node at which the potential originally should quickly rise ending up erroneously rising slowly and being finally determined to an erroneous logic value.
Even in the case of either variation of the circuit constant or coupling noise, the essential problem thereof resides in the NMOS transistors NT43 and NT44 having the function of separating the sense amplifier 42 and the logic tree 41.
In the process of the logic determination operation, the voltages applied to the gate terminals of these NMOS transistors NT43 and NT44 are of an extent a little larger than the threshold voltage of the NMOS transistor, therefore the conduction resistances of these NMOS transistors are considerably larger than that of the NMOS transistor which is usually ON.
The magnitude of the conduction resistance is a cause of the inability to absorb the incorrect potential fluctuation produced due to the coupling noise.
A first object of the present invention is to provide a logic circuit attempting to eliminate the glitches which had occurred in a static CMOS logic circuit to lower the power consumption or to enable realization of a high speed operation by making good use of the characteristics of a dynamic logic circuit by a combination of a logic tree, sense amplifier, and SR latch.
Further, a second object of the present invention is to provide a logic circuit providing a dual-rail type logic tree so as to discard the mechanism for generating a pulse having a short width such as a PDN-F/F logic circuit and capable of facilitating design by automatic placement and routing by CAD.
Further, a third object of the present invention is to provide a logic circuit making the dependency of the operation speed with respect to the height of the logic tree and the gate width of the MOS inside the logic tree smaller than that of the SA-F/F logic circuit and thus capable of realizing high speed operation even if a complex logical function having many input signals is realized.
Further, a fourth object of the present invention is to provide a logic circuit resistant to variations in the circuit constant and coupling noise and capable of realizing stabler operation than that by a DCSL circuit.
According to a first aspect of the present invention, there is provided a logic circuit for outputting logical function evaluation results in synchronization with a synchronization signal, comprising a dual-rail type logic tree forming a path through which only one rail reaches a reference potential according to an input signal and realizing an intended logical function; a sensing latch unit having a first logic input node and a second logic input node receiving a first logic output and a second logic output of the dual-rail type logic tree, a first logic output node, a second logic output node, a sense amplifier which operates upon receipt of the synchronization signal indicating drive and finally sets the logic potentials of the first logic output and the second logic output at different first level and second level according to a difference of conduction resistances possessed by the first logic input and the second logic input which are input to the first logic input node and the second logic input node, a first switching means for short-circuiting the first logic output node and the second logic output node when receiving a synchronization signal indicating an idle stage, a second switching means for electrically connecting or disconnecting the first logic input node and the first logic output node according to the potential of a control terminal, a third switching means for electrically connecting or disconnecting the second logic input node and the second logic output node according to the potential of the control terminal, and a logic tree disconnection controlling means which has a first setting means for setting the potential of the control node connected to the control terminals of the second switching means and the third switching means to a potential that at least enables the connection between two terminals to which the second and third switching means are connected at a stage including the idle stage where the logic has not been finally determined in the sense amplifier, and a second setting means for setting the potential of the control node at a potential that at least enables the disconnection between the two terminals to which the second and third switching means are connected according to the first logic output node or the second logic output node at a stage where the logic is finally determined in the sense amplifier; and a set and reset latch unit for receiving the first logic output of the sensing latch unit at its set terminal, receiving the second logic output of the sensing latch unit at its reset terminal, and holding the logic output of the sensing latch unit for a period of one cycle of the synchronization signal.
Further, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fourth switching means which is connected between a first power source potential capable of placing the second switching means and the third switching means into a connection state and the control node and becomes conductive upon receipt of the synchronization signal indicating the idle stage at its control terminal, and the second setting means of the logic tree disconnection controlling means includes a fifth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into a disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at a first level and a sixth switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fourth switching means which is connected between the first power source potential capable of placing the second switching means and the third switching means into a connection state and the control node and becomes conductive upon receipt of a synchronization signal indicating an idle stage at its control terminal, and the second setting means of the logic tree disconnection controlling means includes a fifth switching means which is connected between an intermediate node and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, a sixth switching means which is connected between the intermediate node and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level, and a seventh switching means which is connected between the second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the intermediate node, is held in a non-conductive state when the fourth switching means is conductive, and becomes conductive when the fourth switching means is held in the non-conductive state.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fourth switching means and a fifth switching means which are connected in series between a first power source potential capable of placing the second switching means and the third switching means into the connection state and a control node and becomes conductive upon receipt of the potential of the first logic output node and the potential of the second logic output node at their control terminals in the idle stage, and the second setting means of the logic tree disconnection controlling means includes a sixth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, and a seventh switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
According to a second aspect of the present invention, there is provided a logic circuit for outputting logical function evaluation results in synchronization with a synchronization signal, comprising a dual-rail type logic tree for forming a path through which only one rail reaches the reference potential according to the input signal and realizing the intended logical function; a sensing latch unit having a first logic input node and a second logic input node receiving a first logic output and a second logic output of the dual-rail type logic tree, a first logic output node, a second logic output node, a sense amplifier which operates upon receipt of a synchronization signal indicating drive and finally sets logic potentials of the first logic output and the second logic output at a different first level and second level according to the difference of conduction resistances possessed by the first logic input and the second logic input which are input to the first logic input node and the second logic input node, a first switching means for short-circuiting the first logic output node and the second logic output node when receiving a synchronization signal indicating an idle stage, a second switching means for electrically connecting or disconnecting the first logic input node and the first logic output node according to the potential of the control terminal, a third switching means for electrically connecting or disconnecting the second logic input node and the second logic output node according to the potential of the control terminal, and a logic tree disconnection controlling means which has a first setting means for setting the potential of the control node connected to the control terminals of the second switching means and the third switching means to a potential that at least enables the connection between two terminals to which the second and third switching means are connected at a stage including the idle stage where the logic has not been finally determined in the sense amplifier, and a second setting means for setting the potential of the control node to a potential that at least enables the disconnection between the two terminals to which the second and third switching means are connected according to the first logic output node or the second logic output node at a stage where the logic is finally determined in the sense amplifier; a set and reset latch unit for receiving a first logic output of the sensing latch unit at its set terminal, receiving a second logic output of the sensing latch unit at its reset terminal, and holding the logic output of the sensing latch unit for a period of one cycle of the synchronization signal; and a fourth switching means which electrically disconnects the path reaching the reference potential of the dual-rail type logic tree and the reference potential in the idle stage and connects them at times other than the idle stage.
Further, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fifth switching means which is connected between the first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and becomes conductive upon receipt of a synchronization signal indicating the idle stage at its control terminal, and the second setting means of the logic tree disconnection controlling means includes a sixth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into a disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, and a seventh switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fifth switching means which is connected between a first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and becomes conductive upon receipt of a synchronization signal indicating the idle stage at its control terminal, and the second setting means of the logic tree disconnection controlling means includes a sixth switching means which is connected between an intermediate node and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, a seventh switching means which is connected between the intermediate node and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level, and an eighth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into a disconnection state and the intermediate node, is held in the non-conductive state when the fifth switching means Is conductive, and becomes conductive when the fifth switching means is held in the non-conductive state.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a fifth switching means and a sixth switching means which are connected in series between a first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and become conductive upon receipt of the potential of the first logic output node and the potential of the second logic output node at their control terminals in the idle stage, and the second setting means of the logic tree disconnection controlling means includes a seventh switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, and an eighth switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
According to a third aspect of the present invention, there is provided a logic circuit for outputting logical function evaluation results in synchronization with a synchronization signal, comprising a dual-rail type logic tree forming a path through which only one rail reaches the reference potential according to an input signal and realizing the intended logical function; a sensing latch unit having a first logic input node and a second logic input node receiving a first logic output and a second logic output of the dual-rail type logic tree, a first logic output node, a second logic output node, a sense amplifier which operates upon receipt of a synchronization signal indicating drive and finally determines the logic potentials of the first logic output and the second logic output at a different first level and second level according to the difference of conduction resistances possessed by the first logic input and the second logic input which are input to the first logic input node and the second logic input node, a first switching means for short-circuiting the first logic output node and the second logic output node when receiving a synchronization signal indicating an idle stage, a second switching means for electrically connecting or disconnecting the first logic input node and the first logic output node according to the potential of the control terminal, a third switching means for electrically connecting or disconnecting the second logic input node and the second logic output node according to the potential of the control terminal, and a logic tree disconnection controlling means which has a first setting means for setting the potential of the control node connected to the control terminals of the second switching means and the third switching means to a potential that at least enables the connection between two terminals to which the second and third switching means are connected at a stage including the idle stage where the logic has not been finally determined in the sense amplifier, and a second setting means for setting the potential of the control node to a potential that at least enables the disconnection between two terminals to which the second and third switching means are connected according to the potential of the first logic output node or the second logic output node at a stage where the logic is finally determined in the sense amplifier; a set and reset latch unit for receiving a first logic output of the sensing latch unit at its set terminal, receiving a second logic output of the sensing latch unit at its reset terminal, and holding the logic output of the sensing latch unit for a period of one cycle of the synchronization signal; a fourth switching means which electrically disconnects the path reaching the reference potential of the dual-rail type logic tree and the reference potential in the idle stage and connects them at times other than the idle stage; and a fifth switching means which forcibly connects the path reaching the reference potential of the dual-rail type logic tree and the reference potential for a period during which the path reaching the reference potential of the dual-rail type logic tree and the reference potential are disconnected by the fourth switching means in the idle stage and when the synchronization signal is stopped while indicating the idle stage as it is.
Further, in the present invention, the first setting means of the logic tree disconnection controlling means includes a sixth switching means which is connected between a first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and becomes conductive upon receipt of a synchronization signal indicating the idle stage at its control terminal, and the second setting means of the logic disconnection controlling means includes a seventh switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, and an eighth switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a sixth switching means which is connected between a first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and becomes conductive upon receipt of a synchronization signal indicating the idle stage at its control terminal, and the second setting means of the logic tree disconnection controlling means includes a seventh switching means which is connected between an intermediate node and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, an eighth switching means which is connected between the intermediate node and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level, and a ninth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the intermediate node, is held in the non-conductive state when the sixth switching means is conductive, and becomes conductive when the sixth switching means is held in the non-conductive state.
Alternatively, in the present invention, the first setting means of the logic tree disconnection controlling means includes a sixth switching means and a seventh switching means which are connected in series between a first power source potential capable of placing the second switching means and the third switching means into the connection state and the control node and become conductive upon receipt of the potential of the first logic output node and the potential of the second logic output node at their control terminals in the idle stage, and the second setting means of the logic tree disconnection controlling means includes an eighth switching means which is connected between a second power source potential capable of placing the second switching means and the third switching means into the disconnection state and the control node, has a control terminal connected to the first logic output node, and becomes conductive when the first logic output potential is at the first level, and a ninth switching means which is connected between the second power source potential and the control node, has a control terminal connected to the second logic output node, and becomes conductive when the second logic output potential is at the first level.
Further, in each logic circuit according to the present invention, the sense amplifier of the sensing latch unit has a first inverter and a second inverter, the output of the first inverter and the input of the second inverter are connected, the connection point thereof is connected to the first logic output node, the input of the first inverter and the output of the second inverter are connected, the connection point thereof is connected to the second logic output node, and the first switching means is connected between the input of the first inverter and the input of the second inverter.
According to the present invention, in the sensing latch unit, where for example the synchronization signal has the logic xe2x80x9c0xe2x80x9d indicating the idle stage, the sense amplifier does not have a driving capability, and the first switching means, the second switching means and the third switching means become the conductive state.
As a result, in the sensing latch unit, a state where all of the first logic input node to which the first logic output of the logic tree is input, the second logic input node to which the second logic output of the logic tree is input, the first logic output node for outputting the first logic output to the set and reset latch unit, and the second logic output node for outputting the second logic output to the set and reset latch unit are short-circuited is exhibited.
In a drive stage immediately after the synchronization signal changes from the logic xe2x80x9c0xe2x80x9d to the logic xe2x80x9c1xe2x80x9d from this idle stage, the sense amplifier has a driving capability, the first switching means becomes the non-conductive state, and the second and third switching means are held in the conductive state as they are.
Accordingly, in this drive stage, the first logic output node and first logic input node and the second logic output node and second logic input node are short-circuited. Further, a state where the first logic output node and first logic input node and the second logic output node and second logic input node in the short-circuited state are released is exhibited.
During the period where the synchronization signal after the final determination of the logic value has the logic xe2x80x9c1xe2x80x9d (final determination stage), the sense amplifier has a driving capability, and a state where the first logic output node and first logic input node and the second logic output node and second logic input node are all cut off is exhibited.
Further, according to the present invention, it is possible to prevent the logic tree and the reference potential from being electrically cut off by the fourth switching means during the period where the synchronization signal becomes the logic xe2x80x9c0xe2x80x9d (idle stage) and the charges in the sensing latch unit and the dual-rail type logic tree from escaping to the reference potential, that is, the ground.
Due to this, a reduction of the power consumption can be achieved.
Further, according to the present invention, where for example the synchronization signal stops at the logic xe2x80x9c0xe2x80x9d and the fourth switching means continuously becomes the non-conductive state, the fifth switching means is held in the conductive state.
Due to this, the internal nodes in the sensing latch unit and the dual-rail type logic tree can be fixed to the potential of the complete logic xe2x80x9c0xe2x80x9d. As a result, a reduction of the leakage current at the set and reset latch unit can be achieved.